1. Field of the Invention
The invention relates to high speed data processing systems, and more particularly to pulse stretching architectures for phase alignment for high speed data acquisition.
2. Background Art
High speed data processing systems, such as high speed data acquisition systems frequently require adjustments to the phases of clocks used to sample incoming data. A failure to properly adjust the phases of clocks can lead to high bit error rates and degrade system performance. For example, if low speed data is serialized in later stages of a data acquisition system, then all higher speed clock phases used in the later stages that require a fixed timing relationship with the first sample clock, are required to be adjusted accordingly.
Existing systems and methods to ensure the proper phase of sampling clocks are often complicated and use excessive power. For example, one approach uses multiplexers and counters to choose the right phase to be used for each of the sampling clock signals. This approach requires many extra circuits and power consumption is relatively high. In another approach a phase rotator and digital logic are used to select the clock phase of the sampling clocks. Using this approach, the resulting circuitry is often very complicated and therefore costly to implement.
What are needed are pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisition.